Find your pillar.
Every story I cover lives inside a pillar. Pillars are long-running, continuously-updated topic hubs — not feeds. Pick one to dive in, or browse by sub-topic or company below.
Where the work lives.
In-memory computing: analog and digital compute-in-memory for AI inference
Tracks analog and digital compute-in-memory architectures that perform matrix operations directly in SRAM, DRAM, or resistive arrays, eliminating the energy cost of shuttling weights between memory and logic.
Carbon nanotubes in energy storage
Carbon nanotubes form percolating networks at sub-1% loadings, delivering 13-fold conductivity improvements over carbon black while enabling higher energy density and faster charging in lithium-ion batteries.
Carbon nanotubes in computing: transistors, interconnects and the path beyond silicon CMOS
Carbon nanotube transistors show higher on-current and lower power-delay than silicon FinFETs, but require solving metallic-tube removal, contact resistance, and alignment challenges before foundry integration.
HBM4 memory supply crunch
The HBM4 supply crunch stems from yield and qualification challenges rather than capacity limits, with producers showing divergent manufacturing maturity that creates structural allocation advantages.
The power wall
Data centers vs. the grid: where the next trillion AI watts actually come from. SMRs, gas peakers, behind-the-meter, and the slow violence of interconnect queues.
The AI memory bottleneck
The constraint that's quietly reshaping the trillion-dollar AI compute build-out: explained, tracked, and updated as it evolves. Six solution paths, four still unresolved.
Export controls & the new silicon geopolitics
The expanding chokepoints between the US, China, and the supply chain caught in the middle: license-by-license, with implementation reality vs. headline reality tracked.
The model-weight perimeter
Securing what's now the most valuable IP on the planet — and failing to. The technical, organizational, and legal infrastructure for keeping frontier model weights in (or out of) the wrong hands.
The advanced packaging race
CoWoS, EMIB, SoIC. Why the assembly line, not the fab, became the new bottleneck, and which packaging architectures will define the next decade.
The post-cloud cloud
Neoclouds, sovereign clouds, and the unraveling of the AWS-GCP-Azure trio. Who's building the infrastructure layer for the next ten years, and where the margin pools are migrating.
Browse by sub-topic.
HBM
High-bandwidth memory ramps, qualifications, allocation.
9 articles · across 4 pillarsCoWoS
TSMC's advanced packaging line: capacity, queue, customers.
2 articles · across 2 pillarsInference economics
Tokens-per-dollar, hardware-software co-design, margin.
1 articles · 1 pillarHyperscaler ASICs
TPU, Trainium, MTIA, Maia: what's shipping and what's not.
1 articles · 1 pillarQuantization
FP8, INT4, MXFP, and the precision-vs-quality frontier.
1 articles · 1 pillarSMR & nuclear
Small modular reactors, PPA economics, build timelines.
0 articles · across 0 pillarsSilicon photonics
Co-packaged optics, and when it actually matters.
0 articles · across 0 pillarsRetrieval & context
RAG architectures, long-context economics, KV caching.
0 articles · across 0 pillarsSovereign AI
National compute strategies and the politics of allocation.
0 articles · across 0 pillarsLiquid cooling
Direct-to-chip and immersion: the new data-center thermal stack.
0 articles · across 0 pillarsEUV & below
High-NA, ASML cycle dynamics, advanced-node economics.
0 articles · across 0 pillarsOpen weights
Llama, DeepSeek, Mistral, and the parallel ecosystem.
0 articles · across 0 pillars