- CNT transistors achieve 1.3 mA/µm on-current, exceeding silicon FinFETs at equivalent gate lengths through aligned arrays of 100-200 tubes per micrometer.
- Contact resistance reaches 6.5 kΩ quantum limit with palladium side contacts at 10nm length, enabling high-performance device scaling.
- MIT built 16-bit RISC-V processor with >14,000 CNTFETs, demonstrating wafer-scale integration with DREAMER design methodology removing metallic tubes.
- Gate delays of 9.86 ps on glass substrates match 90nm silicon node performance using 250nm gate-length aligned CNT FETs.
Framing
Why carbon nanotubes matter for post-silicon computing
Carbon nanotube transistors have demonstrated on-state currents exceeding 1.3 milliamperes per micrometer and transconductance of 0.9 millisiemens per micrometer at 1 volt supply, outperforming commercial silicon MOSFETs at similar gate lengths, yet wafer-scale manufacturing with sub-parts-per-million metallic nanotube contamination remains unsolved.
Silicon transistor scaling no longer yields historical energy-efficiency benefits, spurring research toward carbon nanotube field-effect transistors (CNTFETs), which promise substantial energy-efficiency gains but face intrinsic nanoscale defects and variability that have precluded very-large-scale integration. The materials challenge is fundamental: contact resistance at the metal-to-nanotube interface remains a leading factor in determining overall transistor performance, with palladium contacts achieving the quantum limit of 6.5 kilohms per nanotube at 10-nanometer contact length for p-type side contacts, though this needs higher yield and reproducibility.
Exploiting the advantages of semiconducting CNTs requires overcoming several materials science hurdles. Just as silicon must be purified and doped to be a useful channel material, as-synthesized CNTs can be either metallic or semiconducting and must be purified into semiconducting-only for use in transistors.Authors of review article in Science, Carbon nanotube transistors: Making electronics from molecules, published 2022
Aligned carbon nanotube arrays on glass wafers have achieved 9.86 picosecond gate delays in 250-nanometer gate-length transistors, matching performance of silicon devices at the 90-nanometer node. Progress on transistors alone does not address why memory bandwidth is the real bottleneck in modern computing, but CNT interconnects offer a path to lower resistance wiring at nanoscale dimensions.
How carbon nanotube field-effect transistors achieve sub-10-picosecond switching
Aligned semiconducting nanotubes on glass wafers deliver gate delays that match 90 nm silicon nodes at 250 nm feature sizes, demonstrating a three- to four-generation performance advantage through quantum-confined carrier transport.
A carbon nanotube field-effect transistor operates by modulating current flow through a semiconducting nanotube channel using an electric field applied to a gate electrode. When voltage is applied to the gate, it creates an electric field that either accumulates or depletes charge carriers in the one-dimensional nanotube, switching the device between conducting and insulating states. Aligned carbon nanotube arrays on glass wafers achieved a record gate delay of 9.86 picoseconds with 250 nm gate lengths, matching the performance of 90 nm node silicon devices and demonstrating a three- to four-generation performance advantage. The performance advantage stems from the nanotube's quantum-confined electronic structure and ballistic transport over short channel lengths. Flexible CNT thin-film transistors on polyimide substrates achieved current densities exceeding 17 microamperes per micrometer, on/off ratios greater than 10^6, subthreshold slopes below 200 millivolts per decade, and field-effect mobilities around 50 square centimeters per volt-second. Palladium contacts achieved the quantum limit of 6.5 kilohms per CNT at 10 nm contact length for p-type side contacts, though higher yield and reproducibility remain necessary.
Carbon nanotube transistor performance metrics across device architectures
Industry solutions in flight.
The approaches being pursued in parallel, with the status of each.
CNT transistor on-current
Aligned carbon nanotube field-effect transistors achieved 1.3 milliamperes per micrometer on-state current at 1 volt, exceeding commercial silicon MOSFETs. Stanford demonstrated a 16-bit RISC-V microprocessor with over 14,000 complementary CNT transistors.
CNT FET glass substrate performance
A 2024 study on glass wafer substrates demonstrated CNT FETs with performance matching 90-nanometer-node silicon devices, advancing substrate compatibility for carbon nanotube transistor integration.
CNT transconductance advancement
A 2024 Nature Electronics paper reported high transconductance of 0.9 millisiemens per micrometer using dense CNT arrays with directly grown gate dielectrics, improving device efficiency.
How the story evolved.
A dated log of material developments, each entry linked to its primary source.
Stanford University fabricated a 16-bit RISC-V microprocessor containing more than 14,000 complementary CNFETs using industry-standard design flows and processes, validating a practical path toward beyond-silicon systems. The device executes standard 32-bit instructions on 16-bit data and addresses, demonstrating that carbon nanotube transistor technology can support functional, general-purpose computing architectures.
Key players.
Stanford University
Demonstrated 14,000+ CNTFET 16-bit RISC-V microprocessor (Nature 2019). Leads transistor design, manufacturing methodology, and contact engineering under H.-S. Philip Wong and Subhasish Mitra.
Outlook · what to watch.
The catalysts that will show whether this is closing, holding, or worsening.
16-bit RISC-V microprocessor from CNTs
Stanford University and MIT researchers demonstrated a 16-bit RISC-V microprocessor built entirely from more than 14,000 complementary carbon nanotube field-effect transistors, published in Nature on September 4, 2019. This proved CNT logic circuits could scale to practical complexity.
High-density CNT arrays on silicon wafers
Scientists demonstrated high-density semiconducting carbon nanotube arrays with 100 to 200 nanotubes per micrometer on 10-centimeter silicon wafers, with top-gate field-effect transistors showing on-state current of 1.3 milliamperes per micrometer and transconductance of 0.9 millisiemens per micrometer, published in Science.
Sub-10 nm contact length CNT transistors
Researchers achieved carbon nanotube transistors scaled to sub-10 nm contact lengths using full-contact structures to improve integration density, reported in Nature Electronics in 2023. This addresses a key bottleneck in CNT device miniaturization and density.
Aligned CNTs with 90 nm silicon performance
Peking University reported aligned carbon nanotube field-effect transistors on glass wafers with 250 nm gate length achieving performance equivalent to 90 nm node silicon devices and a record gate delay of 9.86 picoseconds, published in Science Advances. This demonstrates CNTs matching legacy silicon nodes.
Directly grown gate dielectrics on CNT arrays
Researchers created carbon nanotube transistors with transconductance performance using dense arrays and directly grown gate dielectrics that conformably coat the nanotube array, reported in Nature Electronics in 2024. Conformal dielectrics improve electrostatic control and reduce parasitic capacitance.