Micron, year of the ramp. The "American HBM" trade is now structural, not speculative.

Micron Technology plans to double its high-bandwidth memory production capacity to approximately 100,000 wafers per month by the end of 2026, according to Electronic Times, citing industry sources familiar with the company's equipment orders. The expansion narrows a capacity gap that has kept the U.S. chipmaker in third place behind Samsung Electronics and SK Hynix, each of which operates at 150,000 to 200,000 wafers per month. Micron's net addition of up to 60,000 wafers per month this year exceeds its entire 2025 output of 40,000 to 50,000 wafers per month, with equipment deliveries underway at its Taiwan and Singapore fabrication facilities.

The ramp centers on 12-layer HBM4, the memory generation shipping into NVIDIA's Vera Rubin AI accelerator platform. Micron began HBM4 mass production in the second quarter of 2026 and crossed $1 billion in cumulative HBM4 revenue by June, CEO Sanjay Mehrotra said during the company's fiscal third-quarter earnings call. Mehrotra told investors the HBM4 production ramp is progressing roughly twice as fast as the prior-generation HBM3E ramp, with 12-layer HBM4 expected to reach 50 percent of Micron's total HBM output by year-end, up from 20 to 30 percent in early 2026, Electronic Times reported.

All three vendors qualified, for the first time

HBM4 marks the first memory generation in which all three suppliers achieved qualification and began production at the start of the commercial ramp. Silicon Analysts documented the timeline: Micron shipped HBM4 samples in June 2025, Samsung and SK Hynix delivered paid samples between October and December 2025, and NVIDIA CEO Jensen Huang confirmed in June 2026 that all three vendors had qualified for Vera Rubin with third-quarter shipments planned. Micron entered high-volume HBM4 production in March 2026, while Samsung and SK Hynix secured Vera Rubin design wins the same month.

The synchronized qualification changes the competitive question. Through HBM3 and HBM3E, the constraint was binary: a vendor either shipped or did not. Samsung's 18-month qualification struggle for HBM3E, which ran from April 2024 to September 2025, cost the company the entire Blackwell accelerator cycle despite having sufficient wafer capacity. From HBM4 forward, all three suppliers can ship, so the competition shifts to yield, price, and allocation. Silicon Analysts noted that qualification data stops being the whole story once every vendor clears the technical bar.

Micron's qualification velocity improved across successive generations. The company achieved volume production of HBM3E for NVIDIA's H200 by February 2024, earned GB300 certification in April 2025, and began shipping HBM4 samples 14 months later. Silicon Analysts characterized Micron as the late entrant that qualified fast and quietly, a pattern that continued into HBM4 where the company was first to sample publicly.

Capacity gap narrows but remains substantial

Micron's planned expansion to 100,000 wafers per month by the end of 2026 would cut the capacity gap with Samsung and SK Hynix roughly in half, but the company remains the smallest of the three suppliers. Counterpoint Research reported that SK Hynix held 50 percent of the global HBM market in the second quarter of 2026, Samsung held 32 percent, and Micron accounted for 18 percent, according to Electronic Times. The capacity differential explains the share distribution: Samsung and SK Hynix each operate at three to four times Micron's current wafer output.

The expansion is concentrated in facilities outside the United States. Micron is increasing equipment orders to its Tongluo fab in Taiwan and its Woodlands fab in Singapore, with continuous equipment deliveries reported at both sites. Electronic Times noted that investments are also being prepared for Micron's Hiroshima fab in Japan. The company's domestic HBM roadmap follows a different sequence: HyperFRAME Research reported that Micron has prioritized sufficient DRAM wafer capacity in Idaho before adding U.S.-based HBM advanced packaging, meaning domestic wafers precede domestic stacking.

SK Hynix is taking the opposite approach. The company held a groundbreaking ceremony in West Lafayette, Indiana for a packaging and test facility representing more than $4 billion in investment, with cleanroom completion targeted for October 2028 and mass production in the second half of 2029. The site will receive wafers fabricated in Korea, stack and package them into HBM, and ship finished modules to U.S. customers. Samsung's substantial U.S. capacity in Taylor, Texas is foundry-focused, with HBM4 and HBM4E stack work concentrated in Korea. HyperFRAME Research summarized the divergence: one company is onshoring the end of the line, one is building U.S. wafer capacity first, and one is prioritizing foundry over memory packaging.

Supply remains sold out beyond 2027

Micron's HBM3E and HBM4 output is booked under contract through calendar 2027, with demand extending into 2028. The shift to multi-year supply agreements represents a structural change from the historical quarterly negotiation pattern that defined commodity memory markets. EdgeX Exchange noted that customers are securing three-to-five-year contracts, which improves revenue visibility and removes a core component of memory-cycle volatility.

Supply constraints are projected to persist well beyond the current expansion cycle. Micron management stated that tight memory conditions are expected beyond calendar 2027 with no clear visibility on when supply and demand will balance, EdgeX Exchange reported. The durability of the constraint reflects the capital intensity and lead time required to bring new HBM capacity online: new fabs contribute no meaningful volume for 18 to 24 months after groundbreaking.

AI-related memory demand has created persistent supply constraints across the industry, and the constraints operate differently than commodity DRAM oversupply cycles. EdgeX Exchange noted that unlike commodity DRAM, where oversupply can cause prices to fall sharply overnight, HBM operates more like a premium product with limited sources. The multi-year contract structure locks in both demand and pricing frameworks, reducing the risk that new capacity sits idle or that prices collapse when supply increases.

Yield learning curve separates capacity from output

Raw wafer capacity does not translate directly to shippable HBM volume. Qualification, yield learning curves, and 12-layer stacking technology execution matter as much as the number of wafers entering production. Samsung's experience illustrates the constraint: the company had sufficient wafer capacity throughout 2024 and 2025 but could not ship HBM3E in volume to NVIDIA until it cleared qualification in September 2025, 18 months after it began the process. The technical bottleneck cost Samsung the entire Blackwell accelerator cycle despite having more wafer capacity than Micron.

Micron's faster HBM4 ramp reflects both process maturity and stacking technology improvements. The company builds HBM4 on its 1-beta DRAM node, which doubles the memory interface to a 2,048-bit bus and delivers 2.8 terabytes per second of bandwidth per stack. The 12-layer stacking process requires precise alignment and thermal management, and yield improvements take time even after initial qualification. Silicon Analysts noted that the shift from "who can ship?" to "who can ship at yield and price?" makes yield learning curves the next competitive differentiator.

The capacity expansion Micron is executing in 2026 will not contribute to 2026 supply in a meaningful way. New equipment takes months to install, qualify, and ramp to volume production. The 100,000 wafers per month target represents exit-rate capacity at the end of the year, not average capacity across the year. For the entirety of 2026 and into early 2027, Micron operates within a fixed capacity envelope that cannot be expanded quickly, which is why the company's sold-out order book and pricing power remain defensible through the period.

The American HBM trade becomes structural

Micron is the only Western HBM supplier with material production capacity, a position that carries both commercial and policy weight as AI infrastructure spending concentrates in the United States. Macroplane positioned Micron as the anchor of the memory supercycle and the only Western HBM player with material U.S. capacity. The company has committed more than $250 billion in U.S. manufacturing and R&D investment through 2035, up from roughly $200 billion in mid-2025, with domestic HBM advanced packaging sequenced to follow sufficient DRAM wafer capacity in Idaho.

The policy dimension matters because HBM supply is concentrated in two Korean companies and one American company, with no European or Japanese suppliers at volume. Governments purchasing AI infrastructure or subsidizing domestic AI development face a supply base with limited geographic diversity. Micron's capacity expansion and faster qualification cycles reduce, but do not eliminate, the concentration risk. Even at 100,000 wafers per month, Micron will supply roughly one-fifth of the global HBM market, leaving four-fifths in Korea.

The structural trade thesis rests on multi-year contracts and persistent supply constraints, not on speculation about future demand. EdgeX Exchange noted that when customers lock in years of supply, the boom-bust cycle that defined memory for decades gets dampened. The entire 2026 HBM supply is sold out under multi-year contracts, and clients are securing three-to-five-year agreements. That structural shift away from quarterly negotiation improves revenue visibility and removes volatility, turning what was historically a speculative cyclical trade into a capacity-constrained infrastructure play.