The HBM4 spec war: how a memory standard became an NVIDIA-customer fight.

On April 16, 2025, JEDEC ratified the HBM4 standard with a baseline transfer rate of 8 Gb/s per pin and 2 TB/s aggregate bandwidth per stack. The specification doubled the number of independent channels to 32, added directed refresh management for row-hammer mitigation, and maintained backwards compatibility with HBM3 controllers. Barry Wagner, Director of Technical Marketing at NVIDIA and JEDEC HBM Subcommittee Chair, called it a leap forward for AI and accelerated computing. Within months, NVIDIA pushed its suppliers to deliver 13 Gb/s per pin instead, a 62 percent increase over the ratified baseline, according to TrendForce reporting cited by Tom's Hardware. The company's bandwidth target for a 12-high stack escalated from 13 TB/s to 22 TB/s, Blocks and Files reported, forcing Samsung, SK hynix, and Micron to retool designs that had already entered sampling.

NVIDIA disputes the characterization of a delay. A company spokesperson told Tom's Hardware that HBM4 memory partners remain on track for production shipments in the second half of 2026 as originally planned. On June 5, 2026, CEO Jensen Huang stated at Seoul Gimpo that all three vendors have been qualified and are in production. The gap between the JEDEC standard and the deployed product reveals a structural tension: standards bodies set interoperability baselines, but a customer accounting for over 60 percent of global HBM consumption, per Morgan Stanley, can redefine what the market builds.

The spec delta: from JEDEC baseline to NVIDIA custom

JEDEC's HBM4 standard specifies a 2048-bit interface with per-pin speeds starting at 6.4 Gb/s and scaling to 8 Gb/s, yielding 2 TB/s per stack at the upper end. The specification supports 4-high, 8-high, 12-high, and 16-high DRAM stack configurations with 24 Gb or 32 Gb die densities, enabling a maximum cube density of 64 GB for a 32 Gb 16-high configuration. Voltage levels are vendor-specific: VDDQ at 0.7V, 0.75V, 0.8V, or 0.9V, and VDDC at 1.0V or 1.05V, targeting lower power consumption. The 32-channel architecture, double that of HBM3, provides designers with more independent access paths to the memory cube.

NVIDIA's Vera Rubin platform, designed for volume availability in the second half of 2026, requires HBM4 stacks delivering 22 TB/s from a 12-high configuration. That implies per-pin speeds near 13 Gb/s, well above the JEDEC ceiling. Atlas Peak Research documented vendor responses: Samsung achieved 11.7 Gb/s baseline with 13 Gb/s enhancement capability, yielding 3.3 TB/s per stack. Micron reported performance exceeding 11 Gb/s and 2.8 TB/s. SK hynix disclosed speeds above 10 Gb/s but has not published a 13 Gb/s claim. The Rubin NVL72 configuration, with 72 Rubin GPUs and 36 Vera CPUs, requires 20.7 TB of HBM4 across the rack, according to Korea Invest Insights.

The redesign forced on suppliers was not trivial. Each HBM4 stack carries 2,048 data I/Os, so a 13 Gb/s upgrade stresses base die logic, signal integrity, and thermal envelopes. Samsung optimized its design to achieve acceptable yields at the higher speed, Reuters and South Korea Daily reported, and began shipping HBM4 chips to NVIDIA in February 2026. Micron delivered 16-high samples to NVIDIA and stated its full 2026 HBM4 production capacity is sold out. SK hynix, which delivered samples in late 2025, has not disclosed a shipping date but is expected to retain the majority of NVIDIA's allocation through existing contracts.

Why NVIDIA can rewrite the standard after ratification

NVIDIA accounted for over 60 percent of global HBM consumption in 2024, according to Morgan Stanley estimates cited by Tom's Hardware. That purchasing concentration gives the company leverage to shape JEDEC standards, dictate packaging requirements, and pace supplier production cycles. The HBM4 specification was developed with input from NVIDIA engineers, including Barry Wagner, who chairs the JEDEC HBM Subcommittee. Yet the ratified standard reflects a compromise across multiple customers and use cases, not the maximum performance NVIDIA's AI accelerators can absorb.

Counterpoint Research explained that NVIDIA's base die strategy allows it to bypass JEDEC compliance requirements at the interface layer, retaining design control over the logic die that sits beneath the DRAM stack. This architectural choice decouples NVIDIA's roadmap from the standards process, enabling the company to demand custom specs after ratification without waiting for a new JEDEC revision cycle. Suppliers must then decide whether to build to the standard or to the customer's requirements. In a market where NVIDIA's orders fill entire fab lines, the choice is straightforward.

The dynamic also reflects NVIDIA's control over the AI memory ecosystem. TSMC's CoWoS advanced packaging capacity is fully committed to Blackwell and Grace Hopper-class parts, and Rubin's substrate complexity will require expansion at both the foundry and substrate partner levels. By spacing out Rubin's arrival, NVIDIA gives suppliers time to expand interposer and bumping operations without triggering yield degradation or substrate shortages. The delay, whether real or a narrative artifact, aligns Rubin volume with HBM4 readiness and packaging capacity, synchronizing three bottlenecks at once.

Vendor positioning: who benefits from the spec war

SK hynix entered the HBM4 transition as NVIDIA's primary supplier, a relationship that drove the company's market share gains across HBM3 and HBM3E. The NVIDIA partnership positioned SK hynix to capture the majority of high-value AI memory demand, and the company is expected to retain the bulk of NVIDIA's business into 2026 through existing allocation contracts. SK hynix has not publicly claimed 13 Gb/s capability, and its qualification timeline lagged Samsung's by several months.

Samsung passed NVIDIA's HBM4 qualification tests and began shipping in February 2026, according to Blocks and Files. The company's newer base die process and integration stack gave it a slight edge on qualification, and its entry into NVIDIA's supply chain dilutes SK hynix's monopoly premium. Samsung's 11.7 Gb/s baseline with 13 Gb/s enhancement capability positions it to serve both JEDEC-compliant customers and NVIDIA's custom requirements. The company is also supplying AMD with HBM4 chips, broadening its customer base beyond NVIDIA's ecosystem.

Micron, the most recent entrant in the HBM market, delivered 16-high samples to NVIDIA and reported its full 2026 HBM4 production capacity is sold out. The company claims performance exceeding 11 Gb/s and 2.8 TB/s per stack, but it is still building out volume readiness. Micron's capacity constraints limit its near-term allocation share, but the sold-out status signals strong demand across multiple customers. Aju Press reported that Micron is sampling HBM4E parts, the next-generation variant with extended bandwidth ceilings, to NVIDIA, AMD, and custom AI chip designers, positioning the company for the post-2027 transition.

The qualification race also exposes a structural asymmetry: passing NVIDIA's tests does not guarantee equal volume, margin, or strategic positioning. SK hynix maintains majority allocation through incumbency, Samsung's entry creates competitive pressure, and Micron is capacity-constrained. Qualification is a gate, not a guarantee of market share.

Implications for AMD, standards bodies, and the next cycle

NVIDIA may exert outsized influence over HBM4 production, but it is not the only company exposed to the spec war's consequences. AMD's MI400 accelerator is designed around 432 GB of HBM4, a larger memory footprint than NVIDIA's Rubin platform. If HBM4 volume production slips or if suppliers prioritize NVIDIA's orders, AMD's MI400 rollout could face direct pressure. Intel's Habana Gaudi line and other AI accelerator vendors also depend on HBM4 availability, but their purchasing power is an order of magnitude smaller than NVIDIA's.

The episode raises questions about the role of standards bodies in markets dominated by a single buyer. JEDEC ratified HBM4 with input from multiple stakeholders, but the deployed product diverges from the ratified specification. If the standard becomes a baseline that no one ships, its value as an interoperability guarantee diminishes. Suppliers must then maintain two design streams: one for JEDEC compliance and one for NVIDIA's custom requirements. That bifurcation increases engineering overhead and reduces the efficiency gains that standards are meant to provide.

The next cycle, HBM4E, is already in motion. Micron sampled HBM4E parts in mid-2026, and the variant is expected to support 64 GB stacks and bandwidth ceilings above 3.6 TB/s per stack. Aju Press reported that HBM4E is targeting custom AI chip designers and next-generation platforms from NVIDIA and AMD. If the HBM4 pattern repeats, JEDEC will ratify a baseline specification, and NVIDIA will demand performance levels that force another round of redesigns. The question is whether suppliers will preemptively build to NVIDIA's anticipated requirements or wait for formal guidance, and whether other customers will accept the resulting cost and availability trade-offs.